A device of a silicon-on-insulator (SOI) structure is expected to be applicable to micro electro mechanical systems (MEMS) as well as various semiconductor devices such as ultra large scale integrated circuits (LSI), for the device is capable of reducing power consumption, while realizing a high speed operation. In a manufacturing process of a semiconductor device having an SOI structure, a hole or a trench is formed while a silicon (Si) layer formed on a buried oxide (BOX) layer being etched. At this time, a gaseous mixture of SF6+O2, SF6+O2+SiF4, SF6+C4F8 or the like is used as an etching gas, and the Si layer is etched until the BOX layer with the SOI structure is exposed.
However, when the etching is progressed down to near the BOX layer, there occurs a notching phenomenon, i.e., the etching of the silicon layer progresses in a horizontal direction at an interface between the Si layer and the hard BOX layer. It is believed that this notching phenomenon is caused because a balance in inflow of positive ions and electrons is broken at a bottom portion of a hole or a trench with a high aspect ratio, thereby resulting in an excessive presence of the ions. The excessive inflow of the positive ions makes the BOX layer be positively charged, which in turn causes the path of the positive ions among the incident plasma to be bent, resulting in the etching of the sidewall of the silicon layer or a protective film therefor.
Moreover, in general, etching rate at a central portion of a substrate to be processed is different from that at an edge portion thereof. Thus, when etching a silicon layer of a substrate having an SOI structure by using the above mentioned gas system, if the etching is performed until the etching on a lower etching rate portion of the silicon layer is completed, a higher etching rate portion thereof will be kept being etched even after the BOX layer is exposed, resulting in an overetching on that portion. As a result, notching is further likely to occur.
As a technique to prevent notching, there is proposed an etching method for performing an etching by mixing an etching gas with an additive gas such as silicon tetrachloride containing an element identical to that constituting a thin film to be etched (see, for example, Japanese Patent Laid-open Publication No. H8-213368, e.g., claim 1: Reference 1).
Further, there is also proposed an etching method which employs SF6+HBr+O2 as a first etchant and HBr+O2 as a second etchant to prevent notching (see, for example, U.S. Pat. No. 6,391,788, e.g., claim 1: Reference 2).
In general, in the aspect of improving a throughput, a higher etching rate is preferable and, in case of performing an etching on a substrate to be processed with an SOI structure, it is necessary to conduct the processing at a high etching rate. However, both the above-described conventional etching methods aim at avoiding notching at the expense of the etching rate. For example, in Reference 1, though prevention of notching is attempted by forming a protective film through an addition of silicon tetrachloride, the etching rate decreases inevitably due to the presence of the protective film. Further, in the method disclosed in Reference 2, since a gas containing HBr, which forms deposits readily, is used as a first etchant, its etching rate may be in a range between 2 and 4 μm/min at the most, and an etching rate of a second etchant is also as low as 6000 to 8000 Å/min. Accordingly, although the conventional methods for avoiding notching succeed in preventing notching, they have difficulty in finding practical applications, because their etching rates are excessively low.